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c14a89050c
...
cf1af6b412
8 changed files with 64 additions and 255 deletions
201
hence/hence.circ
201
hence/hence.circ
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@ -1,201 +0,0 @@
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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<project source="3.7.2" version="1.0">
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This file is intended to be loaded by Logisim-evolution v3.7.2(https://github.com/logisim-evolution/).
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<lib desc="#Wiring" name="0">
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<tool name="Pin">
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<a name="appearance" val="classic"/>
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</tool>
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</lib>
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<lib desc="#Gates" name="1"/>
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<lib desc="#Plexers" name="2"/>
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<lib desc="#Arithmetic" name="3"/>
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<lib desc="#Memory" name="4"/>
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<lib desc="#I/O" name="5"/>
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<lib desc="#TTL" name="6"/>
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<lib desc="#TCL" name="7"/>
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<lib desc="#Base" name="8"/>
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<lib desc="#BFH-Praktika" name="9"/>
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<lib desc="#Input/Output-Extra" name="10"/>
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<lib desc="#Soc" name="11"/>
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<main name="main"/>
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<options>
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<a name="gateUndefined" val="ignore"/>
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<a name="simlimit" val="1000"/>
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<a name="simrand" val="0"/>
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</options>
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<mappings>
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<tool lib="8" map="Button2" name="Menu Tool"/>
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<tool lib="8" map="Button3" name="Menu Tool"/>
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<tool lib="8" map="Ctrl Button1" name="Menu Tool"/>
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</mappings>
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<toolbar>
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<tool lib="8" name="Poke Tool"/>
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<tool lib="8" name="Edit Tool"/>
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<tool lib="8" name="Wiring Tool"/>
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<tool lib="8" name="Text Tool"/>
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<sep/>
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<tool lib="0" name="Pin"/>
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<tool lib="0" name="Pin">
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<a name="facing" val="west"/>
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<a name="output" val="true"/>
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</tool>
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<sep/>
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<tool lib="1" name="NOT Gate"/>
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<tool lib="1" name="AND Gate"/>
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<tool lib="1" name="OR Gate"/>
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<tool lib="1" name="XOR Gate"/>
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<tool lib="1" name="NAND Gate"/>
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<tool lib="1" name="NOR Gate"/>
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<sep/>
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<tool lib="4" name="D Flip-Flop"/>
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<tool lib="4" name="Register"/>
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</toolbar>
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<circuit name="main">
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<a name="appearance" val="logisim_evolution"/>
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<a name="circuit" val="main"/>
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<a name="circuitnamedboxfixedsize" val="true"/>
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<a name="simulationFrequency" val="1.0"/>
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<comp lib="0" loc="(180,160)" name="Clock">
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<a name="label" val="clk"/>
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</comp>
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<comp lib="0" loc="(380,210)" name="Constant">
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<a name="value" val="0xffff"/>
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<a name="width" val="16"/>
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</comp>
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<comp lib="0" loc="(90,320)" name="Pin">
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<a name="appearance" val="classic"/>
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<a name="label" val="rst"/>
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</comp>
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<comp lib="1" loc="(470,220)" name="NOT Gate"/>
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<comp lib="1" loc="(540,180)" name="AND Gate"/>
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<comp lib="3" loc="(430,220)" name="Comparator">
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<a name="mode" val="unsigned"/>
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<a name="width" val="16"/>
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</comp>
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<comp lib="4" loc="(260,200)" name="Register">
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<a name="appearance" val="logisim_evolution"/>
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<a name="label" val="reg_pc"/>
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<a name="showInTab" val="true"/>
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<a name="width" val="16"/>
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</comp>
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<comp loc="(920,350)" name="memory"/>
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<wire from="(180,160)" to="(490,160)"/>
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<wire from="(290,290)" to="(290,320)"/>
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<wire from="(320,230)" to="(390,230)"/>
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<wire from="(380,210)" to="(390,210)"/>
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<wire from="(430,220)" to="(440,220)"/>
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<wire from="(470,220)" to="(480,220)"/>
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<wire from="(480,200)" to="(480,220)"/>
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<wire from="(480,200)" to="(490,200)"/>
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<wire from="(90,320)" to="(290,320)"/>
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</circuit>
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<circuit name="memory">
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<a name="appearance" val="logisim_evolution"/>
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<a name="circuit" val="memory"/>
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<a name="circuitnamedboxfixedsize" val="true"/>
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<a name="simulationFrequency" val="1.0"/>
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<comp lib="0" loc="(260,220)" name="Pin">
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<a name="appearance" val="NewPins"/>
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<a name="label" val="set"/>
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</comp>
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<comp lib="0" loc="(260,250)" name="Pin">
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<a name="appearance" val="NewPins"/>
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<a name="label" val="clk"/>
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</comp>
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<comp lib="0" loc="(280,160)" name="Pin">
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<a name="appearance" val="NewPins"/>
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<a name="label" val="address"/>
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<a name="radix" val="16"/>
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<a name="width" val="16"/>
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</comp>
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<comp lib="0" loc="(280,190)" name="Pin">
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<a name="appearance" val="NewPins"/>
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<a name="label" val="value"/>
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<a name="radix" val="16"/>
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<a name="width" val="16"/>
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</comp>
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<comp lib="0" loc="(460,420)" name="Constant">
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<a name="value" val="0x8000"/>
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<a name="width" val="16"/>
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</comp>
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<comp lib="0" loc="(460,510)" name="Constant">
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<a name="value" val="0x4000"/>
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<a name="width" val="16"/>
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</comp>
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<comp lib="0" loc="(830,210)" name="Bit Extender">
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<a name="type" val="zero"/>
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</comp>
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<comp lib="0" loc="(970,230)" name="Pin">
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<a name="appearance" val="NewPins"/>
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<a name="facing" val="west"/>
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<a name="label" val="data"/>
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<a name="output" val="true"/>
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<a name="radix" val="16"/>
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<a name="width" val="16"/>
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</comp>
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<comp lib="1" loc="(570,530)" name="AND Gate"/>
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<comp lib="1" loc="(960,230)" name="OR Gate">
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<a name="width" val="16"/>
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</comp>
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<comp lib="3" loc="(510,410)" name="Subtractor">
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<a name="width" val="16"/>
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</comp>
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<comp lib="3" loc="(510,500)" name="Comparator">
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<a name="mode" val="unsigned"/>
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<a name="width" val="16"/>
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</comp>
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<comp lib="4" loc="(540,150)" name="ROM">
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<a name="addrWidth" val="16"/>
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<a name="appearance" val="logisim_evolution"/>
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<a name="contents">addr/data: 16 8
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3 7f fc 86 1 0 1 1
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0 2 85 82 6 0 5 85
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6 0 6 4 0 5 88 4
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0 6 88 89 3 ff ff 86
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32732*0 3 0 4 86
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</a>
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<a name="label" val="program"/>
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<a name="labelvisible" val="true"/>
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</comp>
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<comp lib="4" loc="(640,400)" name="RAM">
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<a name="addrWidth" val="16"/>
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<a name="appearance" val="logisim_evolution"/>
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<a name="dataWidth" val="16"/>
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<a name="enables" val="line"/>
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</comp>
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<wire from="(260,220)" to="(400,220)"/>
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<wire from="(260,250)" to="(390,250)"/>
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<wire from="(280,160)" to="(440,160)"/>
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<wire from="(280,190)" to="(340,190)"/>
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<wire from="(340,190)" to="(340,580)"/>
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<wire from="(340,580)" to="(620,580)"/>
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<wire from="(390,250)" to="(390,550)"/>
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<wire from="(390,550)" to="(520,550)"/>
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<wire from="(400,220)" to="(400,450)"/>
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<wire from="(400,450)" to="(640,450)"/>
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<wire from="(440,160)" to="(440,400)"/>
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<wire from="(440,160)" to="(540,160)"/>
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<wire from="(440,400)" to="(470,400)"/>
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<wire from="(440,460)" to="(440,490)"/>
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<wire from="(440,460)" to="(530,460)"/>
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<wire from="(440,490)" to="(470,490)"/>
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<wire from="(460,420)" to="(470,420)"/>
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<wire from="(460,510)" to="(470,510)"/>
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<wire from="(510,410)" to="(530,410)"/>
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<wire from="(510,510)" to="(520,510)"/>
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<wire from="(530,410)" to="(530,460)"/>
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<wire from="(530,410)" to="(640,410)"/>
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<wire from="(570,530)" to="(590,530)"/>
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<wire from="(590,470)" to="(590,530)"/>
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<wire from="(590,470)" to="(640,470)"/>
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<wire from="(620,490)" to="(620,580)"/>
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<wire from="(620,490)" to="(640,490)"/>
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<wire from="(780,210)" to="(790,210)"/>
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<wire from="(830,210)" to="(910,210)"/>
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<wire from="(880,490)" to="(890,490)"/>
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<wire from="(890,250)" to="(890,490)"/>
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<wire from="(890,250)" to="(910,250)"/>
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<wire from="(960,230)" to="(970,230)"/>
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</circuit>
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</project>
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@ -17,7 +17,7 @@ core:
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.define CORE_MEM_PRG_END, (32 * CORE_KB)
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.define CORE_MEM_ST, CORE_MEM_PRG_END
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.define CORE_MEM_MEM, (40 * CORE_KB)
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.define CORE_MEM_MEM_END, (48 * CORE_KB)
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.define CORE_MEM_MEM_END, (56 * CORE_KB)
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.define CORE_MEM_OUT, CORE_MEM_MEM_END
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.define CORE_MEM_CHR, (CORE_MEM_MEM_END + 1)
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.define CORE_MEM_KEY, (CORE_MEM_MEM_END + 2)
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@ -17,6 +17,7 @@ pub struct Data {
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pub reg_b: u16,
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pub reg_c: u16,
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pub reg_d: u16,
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stack: [u16; 8 * 1024],
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memory: [u16; 16 * 1024],
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term: console::Term,
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}
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@ -35,6 +36,7 @@ impl Data {
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reg_b: 0,
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reg_c: 0,
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reg_d: 0,
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stack: [0; 8 * 1024],
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memory: [0; 16 * 1024],
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term: console::Term::stdout(),
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}
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@ -46,11 +48,11 @@ impl Data {
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Some(val) => Ok(*val as u16),
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None => Ok(0),
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}
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// } else if address < (40 * 1024) {
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// Ok(self.stack[(address - (32 * 1024)) as usize])
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} else if address < (48 * 1024) {
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} else if address < (40 * 1024) {
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Ok(self.stack[(address - (32 * 1024)) as usize])
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} else if address < (56 * 1024) {
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Ok(self.memory[(address - (40 * 1024)) as usize])
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} else if address == (48 * 1024 + 2) {
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} else if address == (56 * 1024 + 2) {
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Ok(self.term.read_char()? as u16)
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} else {
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Ok(0)
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@ -58,14 +60,14 @@ impl Data {
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}
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pub fn set_memory(&mut self, address: u16, value: u16) -> Result<()> {
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// if ((32 * 1024)..(40 * 1024)).contains(&address) {
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// self.stack[(address - (32 * 1024)) as usize] = value;
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if ((32 * 1024)..(48 * 1024)).contains(&address) {
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self.memory[(address - (32 * 1024)) as usize] = value;
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} else if address == (48 * 1024) {
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print!("{}", value);
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if ((32 * 1024)..(40 * 1024)).contains(&address) {
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self.stack[(address - (32 * 1024)) as usize] = value;
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} else if address < (56 * 1024) {
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self.memory[(address - (40 * 1024)) as usize] = value;
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} else if address == (56 * 1024) {
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print!("{value}");
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io::stdout().flush()?;
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} else if address == (48 * 1024 + 1) {
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} else if address == (56 * 1024 + 1) {
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print!("{}", char::from(value as u8));
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io::stdout().flush()?;
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}
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@ -235,12 +237,12 @@ pub fn emulate(data: &mut Data) -> Result<()> {
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match data.reg_opc {
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0x00 => {}
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0x01 => {
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data.memory[data.reg_sp as usize] = data.reg_arg;
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data.stack[data.reg_sp as usize] = data.reg_arg;
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data.reg_sp = data.reg_sp.wrapping_add(1);
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}
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0x02 => {
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data.reg_sp = data.reg_sp.wrapping_sub(1);
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data.memory[data.reg_sp as usize] = 0;
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data.stack[data.reg_sp as usize] = 0;
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}
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0x03 => {
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data.tmp = data.reg_arg;
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|
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@ -249,7 +251,7 @@ pub fn emulate(data: &mut Data) -> Result<()> {
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data.tmp = data.get_register(data.reg_arg as u8);
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}
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0x05 => {
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data.tmp = data.memory[data.reg_sp.wrapping_sub(1) as usize];
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data.tmp = data.stack[data.reg_sp.wrapping_sub(1) as usize];
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}
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0x06 => {
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data.set_register(data.reg_arg as u8, data.tmp);
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@ -260,7 +262,7 @@ pub fn emulate(data: &mut Data) -> Result<()> {
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}
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}
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0x08 => {
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data.memory[data.reg_sp as usize] = data.tmp;
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data.stack[data.reg_sp as usize] = data.tmp;
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data.reg_sp = data.reg_sp.wrapping_add(1);
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}
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// 0x09 => {
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@ -271,7 +273,7 @@ pub fn emulate(data: &mut Data) -> Result<()> {
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0x09 => {
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println!(
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"[DEBUG]: [{}]",
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data.memory.iter().take(data.reg_sp as usize).join(", ")
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data.stack.iter().take(data.reg_sp as usize).join(", ")
|
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);
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print!("Press enter to continue execution...",);
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io::stdout().flush()?;
|
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|
|
|
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2
henceforth/.gitignore
vendored
2
henceforth/.gitignore
vendored
|
|
@ -1,2 +0,0 @@
|
|||
examples/*.asm
|
||||
examples/*.bin
|
||||
43
henceforth/examples/test.asm
Normal file
43
henceforth/examples/test.asm
Normal file
|
|
@ -0,0 +1,43 @@
|
|||
.include "$lib/core.asm"
|
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.include "$lib/std.asm"
|
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.include "$lib/main.asm"
|
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.define MEM_CALL_STACK, CORE_MEM_MEM
|
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.macro stack_transfer_alu
|
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.std_ld
|
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tlr CORE_REG_B
|
||||
.std_ld
|
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tlr CORE_REG_A
|
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.endmacro
|
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.macro call_word, call_word_arg_0_label
|
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ts (OFFSET + 14)
|
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tlr CORE_REG_A
|
||||
ts MEM_CALL_STACK
|
||||
set
|
||||
ts call_word_arg_0_label
|
||||
tlr CORE_REG_PC
|
||||
.endmacro
|
||||
.macro return_word
|
||||
.std_get MEM_CALL_STACK
|
||||
tlr CORE_REG_PC
|
||||
.endmacro
|
||||
.jump_main
|
||||
data:
|
||||
data_strings:
|
||||
words:
|
||||
main:
|
||||
.main main
|
||||
push 10
|
||||
tss
|
||||
tls
|
||||
tss
|
||||
tls
|
||||
.std_ld
|
||||
tlr CORE_REG_A
|
||||
.std_set CORE_MEM_CHR
|
||||
.std_ld
|
||||
tlr CORE_REG_A
|
||||
.std_set CORE_MEM_CHR
|
||||
.std_ld
|
||||
tlr CORE_REG_A
|
||||
.std_set CORE_MEM_CHR
|
||||
.std_stop
|
||||
BIN
henceforth/examples/test.bin
Normal file
BIN
henceforth/examples/test.bin
Normal file
Binary file not shown.
|
|
@ -1 +1 @@
|
|||
1 2 over debug
|
||||
0x0a dup dup emit emit emit
|
||||
|
|
|
|||
|
|
@ -207,40 +207,7 @@ impl compiler::Compilable<compiler::Data, hence::parser::ast::Body> for Instruct
|
|||
arg: None,
|
||||
},
|
||||
]),
|
||||
Instruction::Over => Ok(vec![
|
||||
hence::parser::ast::Node::MacroCall {
|
||||
name: "std_ld".to_string(),
|
||||
args: vec![],
|
||||
},
|
||||
hence::parser::ast::Node::Call {
|
||||
name: "tlr".to_string(),
|
||||
arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
|
||||
},
|
||||
hence::parser::ast::Node::Call {
|
||||
name: "tss".to_string(),
|
||||
arg: None,
|
||||
},
|
||||
hence::parser::ast::Node::Call {
|
||||
name: "tlr".to_string(),
|
||||
arg: Some(hence::arg::Arg::Variable("CORE_REG_B".to_string())),
|
||||
},
|
||||
hence::parser::ast::Node::Call {
|
||||
name: "tsr".to_string(),
|
||||
arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
|
||||
},
|
||||
hence::parser::ast::Node::Call {
|
||||
name: "tls".to_string(),
|
||||
arg: None,
|
||||
},
|
||||
hence::parser::ast::Node::Call {
|
||||
name: "tsr".to_string(),
|
||||
arg: Some(hence::arg::Arg::Variable("CORE_REG_B".to_string())),
|
||||
},
|
||||
hence::parser::ast::Node::Call {
|
||||
name: "tls".to_string(),
|
||||
arg: None,
|
||||
},
|
||||
]),
|
||||
Instruction::Over => Ok(vec![]),
|
||||
Instruction::Rot => Ok(vec![]),
|
||||
Instruction::Nip => Ok(vec![]),
|
||||
Instruction::I => Ok(vec![]),
|
||||
|
|
|
|||
Loading…
Reference in a new issue