diff --git a/hence/hence.circ b/hence/hence.circ deleted file mode 100644 index 057c374..0000000 --- a/hence/hence.circ +++ /dev/null @@ -1,201 +0,0 @@ - - - This file is intended to be loaded by Logisim-evolution v3.7.2(https://github.com/logisim-evolution/). - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - addr/data: 16 8 -3 7f fc 86 1 0 1 1 -0 2 85 82 6 0 5 85 -6 0 6 4 0 5 88 4 -0 6 88 89 3 ff ff 86 -32732*0 3 0 4 86 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/hence/lib/core.asm b/hence/lib/core.asm index b33bc16..88e66e6 100644 --- a/hence/lib/core.asm +++ b/hence/lib/core.asm @@ -17,7 +17,7 @@ core: .define CORE_MEM_PRG_END, (32 * CORE_KB) .define CORE_MEM_ST, CORE_MEM_PRG_END .define CORE_MEM_MEM, (40 * CORE_KB) - .define CORE_MEM_MEM_END, (48 * CORE_KB) + .define CORE_MEM_MEM_END, (56 * CORE_KB) .define CORE_MEM_OUT, CORE_MEM_MEM_END .define CORE_MEM_CHR, (CORE_MEM_MEM_END + 1) .define CORE_MEM_KEY, (CORE_MEM_MEM_END + 2) diff --git a/hence/src/lib/emulator.rs b/hence/src/lib/emulator.rs index ad66d95..8a0a575 100644 --- a/hence/src/lib/emulator.rs +++ b/hence/src/lib/emulator.rs @@ -17,6 +17,7 @@ pub struct Data { pub reg_b: u16, pub reg_c: u16, pub reg_d: u16, + stack: [u16; 8 * 1024], memory: [u16; 16 * 1024], term: console::Term, } @@ -35,6 +36,7 @@ impl Data { reg_b: 0, reg_c: 0, reg_d: 0, + stack: [0; 8 * 1024], memory: [0; 16 * 1024], term: console::Term::stdout(), } @@ -46,11 +48,11 @@ impl Data { Some(val) => Ok(*val as u16), None => Ok(0), } - // } else if address < (40 * 1024) { - // Ok(self.stack[(address - (32 * 1024)) as usize]) - } else if address < (48 * 1024) { + } else if address < (40 * 1024) { + Ok(self.stack[(address - (32 * 1024)) as usize]) + } else if address < (56 * 1024) { Ok(self.memory[(address - (40 * 1024)) as usize]) - } else if address == (48 * 1024 + 2) { + } else if address == (56 * 1024 + 2) { Ok(self.term.read_char()? as u16) } else { Ok(0) @@ -58,14 +60,14 @@ impl Data { } pub fn set_memory(&mut self, address: u16, value: u16) -> Result<()> { - // if ((32 * 1024)..(40 * 1024)).contains(&address) { - // self.stack[(address - (32 * 1024)) as usize] = value; - if ((32 * 1024)..(48 * 1024)).contains(&address) { - self.memory[(address - (32 * 1024)) as usize] = value; - } else if address == (48 * 1024) { - print!("{}", value); + if ((32 * 1024)..(40 * 1024)).contains(&address) { + self.stack[(address - (32 * 1024)) as usize] = value; + } else if address < (56 * 1024) { + self.memory[(address - (40 * 1024)) as usize] = value; + } else if address == (56 * 1024) { + print!("{value}"); io::stdout().flush()?; - } else if address == (48 * 1024 + 1) { + } else if address == (56 * 1024 + 1) { print!("{}", char::from(value as u8)); io::stdout().flush()?; } @@ -235,12 +237,12 @@ pub fn emulate(data: &mut Data) -> Result<()> { match data.reg_opc { 0x00 => {} 0x01 => { - data.memory[data.reg_sp as usize] = data.reg_arg; + data.stack[data.reg_sp as usize] = data.reg_arg; data.reg_sp = data.reg_sp.wrapping_add(1); } 0x02 => { data.reg_sp = data.reg_sp.wrapping_sub(1); - data.memory[data.reg_sp as usize] = 0; + data.stack[data.reg_sp as usize] = 0; } 0x03 => { data.tmp = data.reg_arg; @@ -249,7 +251,7 @@ pub fn emulate(data: &mut Data) -> Result<()> { data.tmp = data.get_register(data.reg_arg as u8); } 0x05 => { - data.tmp = data.memory[data.reg_sp.wrapping_sub(1) as usize]; + data.tmp = data.stack[data.reg_sp.wrapping_sub(1) as usize]; } 0x06 => { data.set_register(data.reg_arg as u8, data.tmp); @@ -260,7 +262,7 @@ pub fn emulate(data: &mut Data) -> Result<()> { } } 0x08 => { - data.memory[data.reg_sp as usize] = data.tmp; + data.stack[data.reg_sp as usize] = data.tmp; data.reg_sp = data.reg_sp.wrapping_add(1); } // 0x09 => { @@ -271,7 +273,7 @@ pub fn emulate(data: &mut Data) -> Result<()> { 0x09 => { println!( "[DEBUG]: [{}]", - data.memory.iter().take(data.reg_sp as usize).join(", ") + data.stack.iter().take(data.reg_sp as usize).join(", ") ); print!("Press enter to continue execution...",); io::stdout().flush()?; diff --git a/henceforth/.gitignore b/henceforth/.gitignore deleted file mode 100644 index 204b6bf..0000000 --- a/henceforth/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -examples/*.asm -examples/*.bin diff --git a/henceforth/examples/test.asm b/henceforth/examples/test.asm new file mode 100644 index 0000000..8325d62 --- /dev/null +++ b/henceforth/examples/test.asm @@ -0,0 +1,43 @@ +.include "$lib/core.asm" +.include "$lib/std.asm" +.include "$lib/main.asm" +.define MEM_CALL_STACK, CORE_MEM_MEM +.macro stack_transfer_alu +.std_ld +tlr CORE_REG_B +.std_ld +tlr CORE_REG_A +.endmacro +.macro call_word, call_word_arg_0_label +ts (OFFSET + 14) +tlr CORE_REG_A +ts MEM_CALL_STACK +set +ts call_word_arg_0_label +tlr CORE_REG_PC +.endmacro +.macro return_word +.std_get MEM_CALL_STACK +tlr CORE_REG_PC +.endmacro +.jump_main +data: +data_strings: +words: +main: +.main main +push 10 +tss +tls +tss +tls +.std_ld +tlr CORE_REG_A +.std_set CORE_MEM_CHR +.std_ld +tlr CORE_REG_A +.std_set CORE_MEM_CHR +.std_ld +tlr CORE_REG_A +.std_set CORE_MEM_CHR +.std_stop \ No newline at end of file diff --git a/henceforth/examples/test.bin b/henceforth/examples/test.bin new file mode 100644 index 0000000..3a9fe76 Binary files /dev/null and b/henceforth/examples/test.bin differ diff --git a/henceforth/examples/test.fth b/henceforth/examples/test.fth index 302576a..8646ba3 100644 --- a/henceforth/examples/test.fth +++ b/henceforth/examples/test.fth @@ -1 +1 @@ -1 2 over debug \ No newline at end of file +0x0a dup dup emit emit emit diff --git a/henceforth/src/lib/compiler/instruction.rs b/henceforth/src/lib/compiler/instruction.rs index 5f011b5..60e34aa 100644 --- a/henceforth/src/lib/compiler/instruction.rs +++ b/henceforth/src/lib/compiler/instruction.rs @@ -207,40 +207,7 @@ impl compiler::Compilable for Instruct arg: None, }, ]), - Instruction::Over => Ok(vec![ - hence::parser::ast::Node::MacroCall { - name: "std_ld".to_string(), - args: vec![], - }, - hence::parser::ast::Node::Call { - name: "tlr".to_string(), - arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())), - }, - hence::parser::ast::Node::Call { - name: "tss".to_string(), - arg: None, - }, - hence::parser::ast::Node::Call { - name: "tlr".to_string(), - arg: Some(hence::arg::Arg::Variable("CORE_REG_B".to_string())), - }, - hence::parser::ast::Node::Call { - name: "tsr".to_string(), - arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())), - }, - hence::parser::ast::Node::Call { - name: "tls".to_string(), - arg: None, - }, - hence::parser::ast::Node::Call { - name: "tsr".to_string(), - arg: Some(hence::arg::Arg::Variable("CORE_REG_B".to_string())), - }, - hence::parser::ast::Node::Call { - name: "tls".to_string(), - arg: None, - }, - ]), + Instruction::Over => Ok(vec![]), Instruction::Rot => Ok(vec![]), Instruction::Nip => Ok(vec![]), Instruction::I => Ok(vec![]),