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Update tlrc opcode

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Dominic Grimm 2022-09-11 09:23:48 +02:00
parent 9a3caf201d
commit 95ff05f154
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GPG key ID: A6C051C716D2CE65
2 changed files with 16 additions and 16 deletions
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30
hence/README.md
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@ -10,18 +10,18 @@
# Opcodes # Opcodes
| Index | Name | Description | Arguments | | Index | Name | Description | Arguments |
| ------ | ------ | ------------------------------------------------------------------ | --------- | | ------ | ------ | ------------------------------------------------------------ | --------- |
| `0x00` | `nop` | No operation | | | `0x00` | `nop` | No operation | |
| `0x01` | `push` | Push to stack | | | `0x01` | `push` | Push to stack | |
| `0x02` | `pop` | Pops top of stack | | | `0x02` | `pop` | Pops top of stack | |
| `0x03` | `ts` | Store value into `tmp` | | | `0x03` | `ts` | Store value into `tmp` | |
| `0x04` | `tsr` | Store register's value into `tmp` | | | `0x04` | `tsr` | Store register's value into `tmp` | |
| `0x05` | `tss` | Stores top of stack into `tmp` | | | `0x05` | `tss` | Stores top of stack into `tmp` | |
| `0x06` | `tlr` | Load `tmp`'s value into register | | | `0x06` | `tlr` | Load `tmp`'s value into register | |
| `0x07` | `tlrc` | Same as `tlr` but only executes if register `a`'s first bit is `1` | | | `0x07` | `tlrc` | Same as `tlr` but only executes if register `tmp`'s first bit is `1` | |
| `0x08` | `tls` | Push value of `tmp` to stack | | | `0x08` | `tls` | Push value of `tmp` to stack | |
| `0x09` | `dbg` | Debug | | | `0x09` | `dbg` | Debug | |
| `0x0a` | `alu` | Runs ALU with `tmp`'s value as operator | | | `0x0a` | `alu` | Runs ALU with `tmp`'s value as operator | |
| `0x0b` | `get` | Sets `tmp` to memory at address in `tmp` | | | `0x0b` | `get` | Sets `tmp` to memory at address in `tmp` | |
| `0x0c` | `set` | Sets memory to value at specific address | | | `0x0c` | `set` | Sets memory to value at specific address | |

2
hence/src/lib/emulator.rs
View file

@ -255,7 +255,7 @@ pub fn emulate(data: &mut Data) -> Result<()> {
data.set_register(data.reg_arg as u8, data.tmp); data.set_register(data.reg_arg as u8, data.tmp);
} }
0x07 => { 0x07 => {
if data.reg_a & 1 == 1 { if data.tmp & 1 == 1 {
data.set_register(data.reg_arg as u8, data.tmp); data.set_register(data.reg_arg as u8, data.tmp);
} }
} }