diff --git a/hence/README.md b/hence/README.md index dadeaea..df9a938 100644 --- a/hence/README.md +++ b/hence/README.md @@ -10,18 +10,18 @@ # Opcodes -| Index | Name | Description | Arguments | -| ------ | ------ | ------------------------------------------------------------------ | --------- | -| `0x00` | `nop` | No operation | | -| `0x01` | `push` | Push to stack | | -| `0x02` | `pop` | Pops top of stack | | -| `0x03` | `ts` | Store value into `tmp` | | -| `0x04` | `tsr` | Store register's value into `tmp` | | -| `0x05` | `tss` | Stores top of stack into `tmp` | | -| `0x06` | `tlr` | Load `tmp`'s value into register | | -| `0x07` | `tlrc` | Same as `tlr` but only executes if register `a`'s first bit is `1` | | -| `0x08` | `tls` | Push value of `tmp` to stack | | -| `0x09` | `dbg` | Debug | | -| `0x0a` | `alu` | Runs ALU with `tmp`'s value as operator | | -| `0x0b` | `get` | Sets `tmp` to memory at address in `tmp` | | -| `0x0c` | `set` | Sets memory to value at specific address | | +| Index | Name | Description | Arguments | +| ------ | ------ | ------------------------------------------------------------ | --------- | +| `0x00` | `nop` | No operation | | +| `0x01` | `push` | Push to stack | | +| `0x02` | `pop` | Pops top of stack | | +| `0x03` | `ts` | Store value into `tmp` | | +| `0x04` | `tsr` | Store register's value into `tmp` | | +| `0x05` | `tss` | Stores top of stack into `tmp` | | +| `0x06` | `tlr` | Load `tmp`'s value into register | | +| `0x07` | `tlrc` | Same as `tlr` but only executes if register `tmp`'s first bit is `1` | | +| `0x08` | `tls` | Push value of `tmp` to stack | | +| `0x09` | `dbg` | Debug | | +| `0x0a` | `alu` | Runs ALU with `tmp`'s value as operator | | +| `0x0b` | `get` | Sets `tmp` to memory at address in `tmp` | | +| `0x0c` | `set` | Sets memory to value at specific address | | diff --git a/hence/src/lib/emulator.rs b/hence/src/lib/emulator.rs index 7877a56..f63b13c 100644 --- a/hence/src/lib/emulator.rs +++ b/hence/src/lib/emulator.rs @@ -255,7 +255,7 @@ pub fn emulate(data: &mut Data) -> Result<()> { data.set_register(data.reg_arg as u8, data.tmp); } 0x07 => { - if data.reg_a & 1 == 1 { + if data.tmp & 1 == 1 { data.set_register(data.reg_arg as u8, data.tmp); } }