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Dominic Grimm 2023-03-24 21:35:06 +01:00
parent cdd5b8855a
commit 5b5886a2f2
Signed by: dergrimm
GPG key ID: 12EFFCAEA9E620BF
2 changed files with 29 additions and 4 deletions
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README.md Normal file
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# hence
Virtual CPU with Assembler and Emulator.
## Architecture
### Memory mapping
| Start | End | Name | Description |
| -------- | -------- | --------------- | ------------------------------------------------------------ |
| `0x0000` | `0x8000` | `PRG` (Program) | ROM of program binary |
| `0x8000` | `0x9fff` | `ST` (Stack) | RAM used as stack |
| `0xa000` | `0xbfff` | `MEM` (Memory) | Generic RAM |
| `0xc000` | | `OUT` (Out) | Writes value as decimal number to standard output when trying to be overwritten |
| `0xc001` | | `CHR` (Char) | Writes value as UTF-8 char to standard output when trying to be overwritten |
| `0xc002` | | `KEY` (Key) | Waits for key press and returns UTF-8 value of it when trying to be read from |
### Registers
| Hex | Name | Description |
| ----- | ---------------------- | ------------------------------ |
| `0x1` | `PC` (Program counter) | Address of current instruction |
| `0x2` | `OPC` | Opcode of current instruction |
| | | |
***TODO***

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hence/lib/core.asm
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.define CORE_MEM_PRG_END, (32 * CORE_KB) .define CORE_MEM_PRG_END, (32 * CORE_KB)
.define CORE_MEM_ST, CORE_MEM_PRG_END .define CORE_MEM_ST, CORE_MEM_PRG_END
.define CORE_MEM_MEM, (40 * CORE_KB) .define CORE_MEM_MEM, (40 * CORE_KB)
.define CORE_MEM_MEM_END, (48 * CORE_KB) .define CORE_MEM_OUT, (48 * CORE_KB)
.define CORE_MEM_OUT, CORE_MEM_MEM_END .define CORE_MEM_CHR, (CORE_MEM_OUT + 1)
.define CORE_MEM_CHR, (CORE_MEM_MEM_END + 1) .define CORE_MEM_KEY, (CORE_MEM_CHR + 2)
.define CORE_MEM_KEY, (CORE_MEM_MEM_END + 2)
.define CORE_REG_PC, 0x0 .define CORE_REG_PC, 0x0
.define CORE_REG_OPC, 0x1 .define CORE_REG_OPC, 0x1