diff --git a/README.md b/README.md
new file mode 100644
index 0000000..52c3156
--- /dev/null
+++ b/README.md
@@ -0,0 +1,26 @@
+# hence
+
+Virtual CPU with Assembler and Emulator.
+
+## Architecture
+
+### Memory mapping
+
+| Start    | End      | Name            | Description                                                  |
+| -------- | -------- | --------------- | ------------------------------------------------------------ |
+| `0x0000` | `0x8000` | `PRG` (Program) | ROM of program binary                                        |
+| `0x8000` | `0x9fff` | `ST` (Stack)    | RAM used as stack                                            |
+| `0xa000` | `0xbfff` | `MEM` (Memory)  | Generic RAM                                                  |
+| `0xc000` |          | `OUT` (Out)     | Writes value as decimal number to standard output when trying to be overwritten |
+| `0xc001` |          | `CHR` (Char)    | Writes value as UTF-8 char to standard output when trying to be overwritten |
+| `0xc002` |          | `KEY` (Key)     | Waits for key press and returns UTF-8 value of it when trying to be read from |
+
+### Registers
+
+| Hex   | Name                   | Description                    |
+| ----- | ---------------------- | ------------------------------ |
+| `0x1` | `PC` (Program counter) | Address of current instruction |
+| `0x2` | `OPC`                  | Opcode of current instruction  |
+|       |                        |                                |
+
+***TODO***
diff --git a/hence/lib/core.asm b/hence/lib/core.asm
index db67b51..a16af68 100644
--- a/hence/lib/core.asm
+++ b/hence/lib/core.asm
@@ -15,10 +15,9 @@
 .define CORE_MEM_PRG_END, (32 * CORE_KB)
 .define CORE_MEM_ST, CORE_MEM_PRG_END
 .define CORE_MEM_MEM, (40 * CORE_KB)
-.define CORE_MEM_MEM_END, (48 * CORE_KB)
-.define CORE_MEM_OUT, CORE_MEM_MEM_END
-.define CORE_MEM_CHR, (CORE_MEM_MEM_END + 1)
-.define CORE_MEM_KEY, (CORE_MEM_MEM_END + 2)
+.define CORE_MEM_OUT, (48 * CORE_KB)
+.define CORE_MEM_CHR, (CORE_MEM_OUT + 1)
+.define CORE_MEM_KEY, (CORE_MEM_CHR + 2)
 
 .define CORE_REG_PC,  0x0
 .define CORE_REG_OPC, 0x1