History

Dominic Grimm e020b8b78a Fixed invalid tests		2022-10-11 16:52:48 +02:00
..
lib	Update memory specs	2022-09-09 14:17:37 +02:00
src	Fixed invalid tests	2022-10-11 16:52:48 +02:00
Cargo.toml	Add string support to henceforth	2022-09-06 11:54:57 +02:00
hence.circ	Update memory specs	2022-09-09 14:17:37 +02:00
README.md	Update README	2022-09-11 16:41:25 +02:00

hence

Registers

Index	Name	Description
`0x00`	`nop`	No operation
`0x01`	`push`	Push to stack
`0x02`	`pop`	Pops top of stack
`0x03`	`ts`	Store value into `tmp`
`0x04`	`tsr`	Store register's value into `tmp`
`0x05`	`tss`	Stores top of stack into `tmp`
`0x06`	`tlr`	Load `tmp`'s value into register
`0x07`	`tlrc`	Same as `tlr` but only executes if register `a`'s first bit is `1`
`0x08`	`tls`	Push value of `tmp` to stack
`0x09`	`dbg`	Debug
`0x0a`	`alu`	Runs ALU with `tmp`'s value as operator
`0x0b`	`get`	Sets `tmp` to memory at address in `tmp`
`0x0c`	`set`	Sets memory to value at specific address