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cf1af6b412 ... c14a89050c

Author SHA1 Message Date
Dominic Grimm
c14a89050c
Update memory specs 2022-09-09 14:17:37 +02:00
Dominic Grimm
54a0f7999b
Update gitignore 2022-09-09 14:17:24 +02:00
Dominic Grimm
c96368c494
Add over word 2022-09-09 14:17:04 +02:00
8 changed files with 255 additions and 64 deletions
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201
hence/hence.circ Normal file
View file

@ -0,0 +1,201 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project source="3.7.2" version="1.0">
This file is intended to be loaded by Logisim-evolution v3.7.2(https://github.com/logisim-evolution/).
<lib desc="#Wiring" name="0">
<tool name="Pin">
<a name="appearance" val="classic"/>
</tool>
</lib>
<lib desc="#Gates" name="1"/>
<lib desc="#Plexers" name="2"/>
<lib desc="#Arithmetic" name="3"/>
<lib desc="#Memory" name="4"/>
<lib desc="#I/O" name="5"/>
<lib desc="#TTL" name="6"/>
<lib desc="#TCL" name="7"/>
<lib desc="#Base" name="8"/>
<lib desc="#BFH-Praktika" name="9"/>
<lib desc="#Input/Output-Extra" name="10"/>
<lib desc="#Soc" name="11"/>
<main name="main"/>
<options>
<a name="gateUndefined" val="ignore"/>
<a name="simlimit" val="1000"/>
<a name="simrand" val="0"/>
</options>
<mappings>
<tool lib="8" map="Button2" name="Menu Tool"/>
<tool lib="8" map="Button3" name="Menu Tool"/>
<tool lib="8" map="Ctrl Button1" name="Menu Tool"/>
</mappings>
<toolbar>
<tool lib="8" name="Poke Tool"/>
<tool lib="8" name="Edit Tool"/>
<tool lib="8" name="Wiring Tool"/>
<tool lib="8" name="Text Tool"/>
<sep/>
<tool lib="0" name="Pin"/>
<tool lib="0" name="Pin">
<a name="facing" val="west"/>
<a name="output" val="true"/>
</tool>
<sep/>
<tool lib="1" name="NOT Gate"/>
<tool lib="1" name="AND Gate"/>
<tool lib="1" name="OR Gate"/>
<tool lib="1" name="XOR Gate"/>
<tool lib="1" name="NAND Gate"/>
<tool lib="1" name="NOR Gate"/>
<sep/>
<tool lib="4" name="D Flip-Flop"/>
<tool lib="4" name="Register"/>
</toolbar>
<circuit name="main">
<a name="appearance" val="logisim_evolution"/>
<a name="circuit" val="main"/>
<a name="circuitnamedboxfixedsize" val="true"/>
<a name="simulationFrequency" val="1.0"/>
<comp lib="0" loc="(180,160)" name="Clock">
<a name="label" val="clk"/>
</comp>
<comp lib="0" loc="(380,210)" name="Constant">
<a name="value" val="0xffff"/>
<a name="width" val="16"/>
</comp>
<comp lib="0" loc="(90,320)" name="Pin">
<a name="appearance" val="classic"/>
<a name="label" val="rst"/>
</comp>
<comp lib="1" loc="(470,220)" name="NOT Gate"/>
<comp lib="1" loc="(540,180)" name="AND Gate"/>
<comp lib="3" loc="(430,220)" name="Comparator">
<a name="mode" val="unsigned"/>
<a name="width" val="16"/>
</comp>
<comp lib="4" loc="(260,200)" name="Register">
<a name="appearance" val="logisim_evolution"/>
<a name="label" val="reg_pc"/>
<a name="showInTab" val="true"/>
<a name="width" val="16"/>
</comp>
<comp loc="(920,350)" name="memory"/>
<wire from="(180,160)" to="(490,160)"/>
<wire from="(290,290)" to="(290,320)"/>
<wire from="(320,230)" to="(390,230)"/>
<wire from="(380,210)" to="(390,210)"/>
<wire from="(430,220)" to="(440,220)"/>
<wire from="(470,220)" to="(480,220)"/>
<wire from="(480,200)" to="(480,220)"/>
<wire from="(480,200)" to="(490,200)"/>
<wire from="(90,320)" to="(290,320)"/>
</circuit>
<circuit name="memory">
<a name="appearance" val="logisim_evolution"/>
<a name="circuit" val="memory"/>
<a name="circuitnamedboxfixedsize" val="true"/>
<a name="simulationFrequency" val="1.0"/>
<comp lib="0" loc="(260,220)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="label" val="set"/>
</comp>
<comp lib="0" loc="(260,250)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="label" val="clk"/>
</comp>
<comp lib="0" loc="(280,160)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="label" val="address"/>
<a name="radix" val="16"/>
<a name="width" val="16"/>
</comp>
<comp lib="0" loc="(280,190)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="label" val="value"/>
<a name="radix" val="16"/>
<a name="width" val="16"/>
</comp>
<comp lib="0" loc="(460,420)" name="Constant">
<a name="value" val="0x8000"/>
<a name="width" val="16"/>
</comp>
<comp lib="0" loc="(460,510)" name="Constant">
<a name="value" val="0x4000"/>
<a name="width" val="16"/>
</comp>
<comp lib="0" loc="(830,210)" name="Bit Extender">
<a name="type" val="zero"/>
</comp>
<comp lib="0" loc="(970,230)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="facing" val="west"/>
<a name="label" val="data"/>
<a name="output" val="true"/>
<a name="radix" val="16"/>
<a name="width" val="16"/>
</comp>
<comp lib="1" loc="(570,530)" name="AND Gate"/>
<comp lib="1" loc="(960,230)" name="OR Gate">
<a name="width" val="16"/>
</comp>
<comp lib="3" loc="(510,410)" name="Subtractor">
<a name="width" val="16"/>
</comp>
<comp lib="3" loc="(510,500)" name="Comparator">
<a name="mode" val="unsigned"/>
<a name="width" val="16"/>
</comp>
<comp lib="4" loc="(540,150)" name="ROM">
<a name="addrWidth" val="16"/>
<a name="appearance" val="logisim_evolution"/>
<a name="contents">addr/data: 16 8
3 7f fc 86 1 0 1 1
0 2 85 82 6 0 5 85
6 0 6 4 0 5 88 4
0 6 88 89 3 ff ff 86
32732*0 3 0 4 86
</a>
<a name="label" val="program"/>
<a name="labelvisible" val="true"/>
</comp>
<comp lib="4" loc="(640,400)" name="RAM">
<a name="addrWidth" val="16"/>
<a name="appearance" val="logisim_evolution"/>
<a name="dataWidth" val="16"/>
<a name="enables" val="line"/>
</comp>
<wire from="(260,220)" to="(400,220)"/>
<wire from="(260,250)" to="(390,250)"/>
<wire from="(280,160)" to="(440,160)"/>
<wire from="(280,190)" to="(340,190)"/>
<wire from="(340,190)" to="(340,580)"/>
<wire from="(340,580)" to="(620,580)"/>
<wire from="(390,250)" to="(390,550)"/>
<wire from="(390,550)" to="(520,550)"/>
<wire from="(400,220)" to="(400,450)"/>
<wire from="(400,450)" to="(640,450)"/>
<wire from="(440,160)" to="(440,400)"/>
<wire from="(440,160)" to="(540,160)"/>
<wire from="(440,400)" to="(470,400)"/>
<wire from="(440,460)" to="(440,490)"/>
<wire from="(440,460)" to="(530,460)"/>
<wire from="(440,490)" to="(470,490)"/>
<wire from="(460,420)" to="(470,420)"/>
<wire from="(460,510)" to="(470,510)"/>
<wire from="(510,410)" to="(530,410)"/>
<wire from="(510,510)" to="(520,510)"/>
<wire from="(530,410)" to="(530,460)"/>
<wire from="(530,410)" to="(640,410)"/>
<wire from="(570,530)" to="(590,530)"/>
<wire from="(590,470)" to="(590,530)"/>
<wire from="(590,470)" to="(640,470)"/>
<wire from="(620,490)" to="(620,580)"/>
<wire from="(620,490)" to="(640,490)"/>
<wire from="(780,210)" to="(790,210)"/>
<wire from="(830,210)" to="(910,210)"/>
<wire from="(880,490)" to="(890,490)"/>
<wire from="(890,250)" to="(890,490)"/>
<wire from="(890,250)" to="(910,250)"/>
<wire from="(960,230)" to="(970,230)"/>
</circuit>
</project>

2
hence/lib/core.asm
View file

@ -17,7 +17,7 @@ core:
.define CORE_MEM_PRG_END, (32 * CORE_KB) .define CORE_MEM_PRG_END, (32 * CORE_KB)
.define CORE_MEM_ST, CORE_MEM_PRG_END .define CORE_MEM_ST, CORE_MEM_PRG_END
.define CORE_MEM_MEM, (40 * CORE_KB) .define CORE_MEM_MEM, (40 * CORE_KB)
.define CORE_MEM_MEM_END, (56 * CORE_KB) .define CORE_MEM_MEM_END, (48 * CORE_KB)
.define CORE_MEM_OUT, CORE_MEM_MEM_END .define CORE_MEM_OUT, CORE_MEM_MEM_END
.define CORE_MEM_CHR, (CORE_MEM_MEM_END + 1) .define CORE_MEM_CHR, (CORE_MEM_MEM_END + 1)
.define CORE_MEM_KEY, (CORE_MEM_MEM_END + 2) .define CORE_MEM_KEY, (CORE_MEM_MEM_END + 2)

34
hence/src/lib/emulator.rs
View file

@ -17,7 +17,6 @@ pub struct Data {
pub reg_b: u16, pub reg_b: u16,
pub reg_c: u16, pub reg_c: u16,
pub reg_d: u16, pub reg_d: u16,
stack: [u16; 8 * 1024],
memory: [u16; 16 * 1024], memory: [u16; 16 * 1024],
term: console::Term, term: console::Term,
} }
@ -36,7 +35,6 @@ impl Data {
reg_b: 0, reg_b: 0,
reg_c: 0, reg_c: 0,
reg_d: 0, reg_d: 0,
stack: [0; 8 * 1024],
memory: [0; 16 * 1024], memory: [0; 16 * 1024],
term: console::Term::stdout(), term: console::Term::stdout(),
} }
@ -48,11 +46,11 @@ impl Data {
Some(val) => Ok(*val as u16), Some(val) => Ok(*val as u16),
None => Ok(0), None => Ok(0),
} }
} else if address < (40 * 1024) { // } else if address < (40 * 1024) {
Ok(self.stack[(address - (32 * 1024)) as usize]) // Ok(self.stack[(address - (32 * 1024)) as usize])
} else if address < (56 * 1024) { } else if address < (48 * 1024) {
Ok(self.memory[(address - (40 * 1024)) as usize]) Ok(self.memory[(address - (40 * 1024)) as usize])
} else if address == (56 * 1024 + 2) { } else if address == (48 * 1024 + 2) {
Ok(self.term.read_char()? as u16) Ok(self.term.read_char()? as u16)
} else { } else {
Ok(0) Ok(0)
@ -60,14 +58,14 @@ impl Data {
} }
pub fn set_memory(&mut self, address: u16, value: u16) -> Result<()> { pub fn set_memory(&mut self, address: u16, value: u16) -> Result<()> {
if ((32 * 1024)..(40 * 1024)).contains(&address) { // if ((32 * 1024)..(40 * 1024)).contains(&address) {
self.stack[(address - (32 * 1024)) as usize] = value; // self.stack[(address - (32 * 1024)) as usize] = value;
} else if address < (56 * 1024) { if ((32 * 1024)..(48 * 1024)).contains(&address) {
self.memory[(address - (40 * 1024)) as usize] = value; self.memory[(address - (32 * 1024)) as usize] = value;
} else if address == (56 * 1024) { } else if address == (48 * 1024) {
print!("{value}"); print!("{}", value);
io::stdout().flush()?; io::stdout().flush()?;
} else if address == (56 * 1024 + 1) { } else if address == (48 * 1024 + 1) {
print!("{}", char::from(value as u8)); print!("{}", char::from(value as u8));
io::stdout().flush()?; io::stdout().flush()?;
} }
@ -237,12 +235,12 @@ pub fn emulate(data: &mut Data) -> Result<()> {
match data.reg_opc { match data.reg_opc {
0x00 => {} 0x00 => {}
0x01 => { 0x01 => {
data.stack[data.reg_sp as usize] = data.reg_arg; data.memory[data.reg_sp as usize] = data.reg_arg;
data.reg_sp = data.reg_sp.wrapping_add(1); data.reg_sp = data.reg_sp.wrapping_add(1);
} }
0x02 => { 0x02 => {
data.reg_sp = data.reg_sp.wrapping_sub(1); data.reg_sp = data.reg_sp.wrapping_sub(1);
data.stack[data.reg_sp as usize] = 0; data.memory[data.reg_sp as usize] = 0;
} }
0x03 => { 0x03 => {
data.tmp = data.reg_arg; data.tmp = data.reg_arg;
@ -251,7 +249,7 @@ pub fn emulate(data: &mut Data) -> Result<()> {
data.tmp = data.get_register(data.reg_arg as u8); data.tmp = data.get_register(data.reg_arg as u8);
} }
0x05 => { 0x05 => {
data.tmp = data.stack[data.reg_sp.wrapping_sub(1) as usize]; data.tmp = data.memory[data.reg_sp.wrapping_sub(1) as usize];
} }
0x06 => { 0x06 => {
data.set_register(data.reg_arg as u8, data.tmp); data.set_register(data.reg_arg as u8, data.tmp);
@ -262,7 +260,7 @@ pub fn emulate(data: &mut Data) -> Result<()> {
} }
} }
0x08 => { 0x08 => {
data.stack[data.reg_sp as usize] = data.tmp; data.memory[data.reg_sp as usize] = data.tmp;
data.reg_sp = data.reg_sp.wrapping_add(1); data.reg_sp = data.reg_sp.wrapping_add(1);
} }
// 0x09 => { // 0x09 => {
@ -273,7 +271,7 @@ pub fn emulate(data: &mut Data) -> Result<()> {
0x09 => { 0x09 => {
println!( println!(
"[DEBUG]: [{}]", "[DEBUG]: [{}]",
data.stack.iter().take(data.reg_sp as usize).join(", ") data.memory.iter().take(data.reg_sp as usize).join(", ")
); );
print!("Press enter to continue execution...",); print!("Press enter to continue execution...",);
io::stdout().flush()?; io::stdout().flush()?;

2
henceforth/.gitignore vendored Normal file
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@ -0,0 +1,2 @@
examples/*.asm
examples/*.bin

43
henceforth/examples/test.asm
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@ -1,43 +0,0 @@
.include "$lib/core.asm"
.include "$lib/std.asm"
.include "$lib/main.asm"
.define MEM_CALL_STACK, CORE_MEM_MEM
.macro stack_transfer_alu
.std_ld
tlr CORE_REG_B
.std_ld
tlr CORE_REG_A
.endmacro
.macro call_word, call_word_arg_0_label
ts (OFFSET + 14)
tlr CORE_REG_A
ts MEM_CALL_STACK
set
ts call_word_arg_0_label
tlr CORE_REG_PC
.endmacro
.macro return_word
.std_get MEM_CALL_STACK
tlr CORE_REG_PC
.endmacro
.jump_main
data:
data_strings:
words:
main:
.main main
push 10
tss
tls
tss
tls
.std_ld
tlr CORE_REG_A
.std_set CORE_MEM_CHR
.std_ld
tlr CORE_REG_A
.std_set CORE_MEM_CHR
.std_ld
tlr CORE_REG_A
.std_set CORE_MEM_CHR
.std_stop

BIN
henceforth/examples/test.bin
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Binary file not shown.

2
henceforth/examples/test.fth
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@ -1 +1 @@
0x0a dup dup emit emit emit 1 2 over debug

35
henceforth/src/lib/compiler/instruction.rs
View file

@ -207,7 +207,40 @@ impl compiler::Compilable<compiler::Data, hence::parser::ast::Body> for Instruct
arg: None, arg: None,
}, },
]), ]),
Instruction::Over => Ok(vec![]), Instruction::Over => Ok(vec![
hence::parser::ast::Node::MacroCall {
name: "std_ld".to_string(),
args: vec![],
},
hence::parser::ast::Node::Call {
name: "tlr".to_string(),
arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
},
hence::parser::ast::Node::Call {
name: "tss".to_string(),
arg: None,
},
hence::parser::ast::Node::Call {
name: "tlr".to_string(),
arg: Some(hence::arg::Arg::Variable("CORE_REG_B".to_string())),
},
hence::parser::ast::Node::Call {
name: "tsr".to_string(),
arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
},
hence::parser::ast::Node::Call {
name: "tls".to_string(),
arg: None,
},
hence::parser::ast::Node::Call {
name: "tsr".to_string(),
arg: Some(hence::arg::Arg::Variable("CORE_REG_B".to_string())),
},
hence::parser::ast::Node::Call {
name: "tls".to_string(),
arg: None,
},
]),
Instruction::Rot => Ok(vec![]), Instruction::Rot => Ok(vec![]),
Instruction::Nip => Ok(vec![]), Instruction::Nip => Ok(vec![]),
Instruction::I => Ok(vec![]), Instruction::I => Ok(vec![]),