1534 lines
64 KiB
Rust
1534 lines
64 KiB
Rust
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use anyhow::{bail, Result};
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use crate::compiler;
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#[derive(Debug, Clone, PartialEq, Eq, Hash)]
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pub enum Instruction {
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Nop,
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Debug,
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Quit,
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Push(i32),
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Drop,
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Depth,
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Pick,
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Dup,
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Swap,
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Over,
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Rot,
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Nip,
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I,
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J,
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Tuck,
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Fetch,
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FetchPrint,
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Store,
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PlusStore,
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MinusStore,
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Cells,
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Allot,
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Dot,
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Emit,
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Space,
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Spaces,
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Cr,
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StringPrint(usize),
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StringReference(usize),
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Count,
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Not,
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And,
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Nand,
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Or,
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Nor,
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Xor,
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Xnor,
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Lsh,
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Rsh,
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Compare,
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Eq,
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Neq,
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Lt,
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Leq,
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Gt,
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Geq,
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Min,
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Max,
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Boolean,
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Invert,
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Random,
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Plus,
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OnePlus,
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TwoPlus,
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Minus,
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OneMinus,
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TwoMinus,
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Times,
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Divide,
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Mod,
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AsmQuote(String),
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Multiple {
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instruction: Box<Self>,
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count: usize,
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},
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Call(String),
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Condition(usize),
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}
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impl compiler::Compilable<compiler::Compiler, hence::parser::ast::Body> for Instruction {
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fn compile(&self, data: &compiler::Compiler) -> Result<hence::parser::ast::Body> {
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match self {
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Instruction::Nop => Ok(vec![hence::parser::ast::Node::Call {
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name: "nop".to_string(),
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arg: None,
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}]),
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Instruction::Debug => Ok(vec![hence::parser::ast::Node::Call {
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name: "dbg".to_string(),
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arg: None,
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}]),
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Instruction::Quit => Ok(vec![hence::parser::ast::Node::MacroCall {
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name: "std_stop".to_string(),
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args: vec![],
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}]),
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Instruction::Push(x) => Ok(vec![hence::parser::ast::Node::Call {
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name: "push".to_string(),
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arg: Some(hence::arg::Arg::Number(*x as u16)),
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}]),
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Instruction::Drop => Ok(vec![hence::parser::ast::Node::Call {
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name: "pop".to_string(),
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arg: None,
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}]),
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Instruction::Depth => Ok(vec![
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hence::parser::ast::Node::Call {
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name: "tsr".to_string(),
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arg: Some(hence::arg::Arg::Variable("CORE_REG_SP".to_string())),
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},
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hence::parser::ast::Node::Call {
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name: "tls".to_string(),
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arg: None,
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},
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]),
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Instruction::Pick => Ok(vec![
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hence::parser::ast::Node::Call {
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name: "tsr".to_string(),
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arg: Some(hence::arg::Arg::Variable("CORE_REG_SP".to_string())),
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},
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hence::parser::ast::Node::Call {
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name: "tlr".to_string(),
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arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
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},
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hence::parser::ast::Node::MacroCall {
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name: "std_ld".to_string(),
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args: vec![],
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},
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hence::parser::ast::Node::Call {
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name: "tlr".to_string(),
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arg: Some(hence::arg::Arg::Variable("CORE_REG_B".to_string())),
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},
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hence::parser::ast::Node::MacroCall {
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name: "std_alu".to_string(),
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args: vec![hence::arg::Arg::Variable("CORE_ALU_SUB".to_string())],
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},
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hence::parser::ast::Node::Call {
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name: "tlr".to_string(),
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arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
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},
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hence::parser::ast::Node::MacroCall {
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name: "std_rset".to_string(),
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args: vec![
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hence::arg::Arg::Variable("CORE_REG_B".to_string()),
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hence::arg::Arg::BinaryExpression {
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left: Box::new(hence::arg::Arg::Variable(
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"CORE_MEM_PRG_END".to_string(),
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)),
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right: Box::new(hence::arg::Arg::Number(2)),
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op: hence::arg::BinaryExpressionOperator::Sub,
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},
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],
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},
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hence::parser::ast::Node::MacroCall {
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name: "std_alu".to_string(),
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args: vec![hence::arg::Arg::Variable("CORE_ALU_ADD".to_string())],
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},
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hence::parser::ast::Node::Call {
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name: "get".to_string(),
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arg: None,
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},
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hence::parser::ast::Node::Call {
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name: "tls".to_string(),
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arg: None,
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},
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]),
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Instruction::Dup => Ok(vec![
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hence::parser::ast::Node::Call {
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name: "tss".to_string(),
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arg: None,
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},
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hence::parser::ast::Node::Call {
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name: "tls".to_string(),
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arg: None,
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},
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]),
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Instruction::Swap => Ok(vec![
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hence::parser::ast::Node::MacroCall {
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name: "std_ld".to_string(),
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args: vec![],
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},
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hence::parser::ast::Node::Call {
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name: "tlr".to_string(),
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arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
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},
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hence::parser::ast::Node::MacroCall {
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name: "std_ld".to_string(),
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args: vec![],
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},
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hence::parser::ast::Node::Call {
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name: "tlr".to_string(),
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arg: Some(hence::arg::Arg::Variable("CORE_REG_B".to_string())),
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},
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hence::parser::ast::Node::Call {
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name: "tsr".to_string(),
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arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
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},
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hence::parser::ast::Node::Call {
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name: "tls".to_string(),
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arg: None,
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},
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hence::parser::ast::Node::Call {
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name: "tsr".to_string(),
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arg: Some(hence::arg::Arg::Variable("CORE_REG_B".to_string())),
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},
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hence::parser::ast::Node::Call {
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name: "tls".to_string(),
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arg: None,
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},
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]),
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Instruction::Over => Ok(vec![
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hence::parser::ast::Node::MacroCall {
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name: "std_ld".to_string(),
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args: vec![],
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},
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hence::parser::ast::Node::Call {
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name: "tlr".to_string(),
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arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
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},
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hence::parser::ast::Node::Call {
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name: "tss".to_string(),
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arg: None,
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},
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hence::parser::ast::Node::Call {
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name: "tlr".to_string(),
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arg: Some(hence::arg::Arg::Variable("CORE_REG_B".to_string())),
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},
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hence::parser::ast::Node::Call {
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name: "tsr".to_string(),
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arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
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},
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hence::parser::ast::Node::Call {
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name: "tls".to_string(),
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arg: None,
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},
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hence::parser::ast::Node::Call {
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name: "tsr".to_string(),
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arg: Some(hence::arg::Arg::Variable("CORE_REG_B".to_string())),
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},
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hence::parser::ast::Node::Call {
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name: "tls".to_string(),
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arg: None,
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},
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]),
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Instruction::Rot => Ok(vec![
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hence::parser::ast::Node::MacroCall {
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name: "std_ld".to_string(),
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args: vec![],
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},
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hence::parser::ast::Node::Call {
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name: "tlr".to_string(),
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arg: Some(hence::arg::Arg::Variable("CORE_REG_B".to_string())),
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},
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hence::parser::ast::Node::MacroCall {
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name: "std_ld".to_string(),
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args: vec![],
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},
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hence::parser::ast::Node::Call {
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name: "tlr".to_string(),
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arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
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},
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hence::parser::ast::Node::MacroCall {
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name: "std_ld".to_string(),
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args: vec![],
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},
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hence::parser::ast::Node::Call {
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name: "tlr".to_string(),
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arg: Some(hence::arg::Arg::Variable("CORE_REG_C".to_string())),
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},
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hence::parser::ast::Node::Call {
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name: "tsr".to_string(),
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arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
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},
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hence::parser::ast::Node::Call {
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name: "tls".to_string(),
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arg: None,
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},
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hence::parser::ast::Node::Call {
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name: "tsr".to_string(),
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arg: Some(hence::arg::Arg::Variable("CORE_REG_B".to_string())),
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},
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hence::parser::ast::Node::Call {
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name: "tls".to_string(),
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arg: None,
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},
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hence::parser::ast::Node::Call {
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name: "tsr".to_string(),
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arg: Some(hence::arg::Arg::Variable("CORE_REG_C".to_string())),
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},
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hence::parser::ast::Node::Call {
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name: "tls".to_string(),
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arg: None,
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},
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]),
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Instruction::Nip => Ok(vec![
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hence::parser::ast::Node::MacroCall {
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name: "std_ld".to_string(),
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args: vec![],
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},
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hence::parser::ast::Node::Call {
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name: "pop".to_string(),
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arg: None,
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},
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hence::parser::ast::Node::Call {
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name: "tls".to_string(),
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arg: None,
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},
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]),
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Instruction::I => Ok(vec![
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hence::parser::ast::Node::MacroCall {
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name: "std_get".to_string(),
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args: vec![hence::arg::Arg::Variable("MEM_LOOP_I".to_string())],
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},
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hence::parser::ast::Node::Call {
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name: "tls".to_string(),
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arg: None,
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},
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]),
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Instruction::J => Ok(vec![
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hence::parser::ast::Node::MacroCall {
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name: "std_get".to_string(),
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args: vec![hence::arg::Arg::Variable("MEM_LOOP_J".to_string())],
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},
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hence::parser::ast::Node::Call {
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name: "tls".to_string(),
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arg: None,
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},
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]),
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Instruction::Tuck => Ok(vec![
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hence::parser::ast::Node::MacroCall {
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name: "std_ld".to_string(),
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args: vec![],
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},
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hence::parser::ast::Node::Call {
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name: "tlr".to_string(),
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arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
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},
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hence::parser::ast::Node::MacroCall {
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name: "std_ld".to_string(),
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args: vec![],
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},
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hence::parser::ast::Node::Call {
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name: "tlr".to_string(),
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arg: Some(hence::arg::Arg::Variable("CORE_REG_B".to_string())),
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},
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hence::parser::ast::Node::Call {
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name: "tsr".to_string(),
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arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
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},
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hence::parser::ast::Node::Call {
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name: "tls".to_string(),
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arg: None,
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},
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hence::parser::ast::Node::Call {
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name: "tsr".to_string(),
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arg: Some(hence::arg::Arg::Variable("CORE_REG_B".to_string())),
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},
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hence::parser::ast::Node::Call {
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|
name: "tls".to_string(),
|
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|
arg: None,
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||
|
},
|
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|
hence::parser::ast::Node::Call {
|
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|
name: "tsr".to_string(),
|
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|
arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
|
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|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tls".to_string(),
|
||
|
arg: None,
|
||
|
},
|
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|
]),
|
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|
Instruction::Fetch => Ok(vec![
|
||
|
hence::parser::ast::Node::MacroCall {
|
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|
name: "std_ld".to_string(),
|
||
|
args: vec![],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "get".to_string(),
|
||
|
arg: None,
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tls".to_string(),
|
||
|
arg: None,
|
||
|
},
|
||
|
]),
|
||
|
Instruction::FetchPrint => Ok(vec![
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_ld".to_string(),
|
||
|
args: vec![],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "get".to_string(),
|
||
|
arg: None,
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tlr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_set".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("CORE_MEM_OUT".to_string())],
|
||
|
},
|
||
|
]),
|
||
|
Instruction::Store => Ok(vec![
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_ld".to_string(),
|
||
|
args: vec![],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tlr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_B".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_ld".to_string(),
|
||
|
args: vec![],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tlr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tsr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_B".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "set".to_string(),
|
||
|
arg: None,
|
||
|
},
|
||
|
]),
|
||
|
Instruction::PlusStore => Ok(vec![
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_ld".to_string(),
|
||
|
args: vec![],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tlr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_C".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "get".to_string(),
|
||
|
arg: None,
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tlr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_ld".to_string(),
|
||
|
args: vec![],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tlr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_B".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_alu".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("CORE_ALU_ADD".to_string())],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tlr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tsr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_C".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "set".to_string(),
|
||
|
arg: None,
|
||
|
},
|
||
|
]),
|
||
|
Instruction::MinusStore => Ok(vec![
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_ld".to_string(),
|
||
|
args: vec![],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tlr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_C".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "get".to_string(),
|
||
|
arg: None,
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tlr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_ld".to_string(),
|
||
|
args: vec![],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tlr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_B".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_alu".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("CORE_ALU_SUB".to_string())],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tlr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tsr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_C".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "set".to_string(),
|
||
|
arg: None,
|
||
|
},
|
||
|
]),
|
||
|
Instruction::Cells => Ok(vec![]),
|
||
|
Instruction::Allot => Ok(vec![
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_get".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("MEM_ALLOC_PTR".to_string())],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tlr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_ld".to_string(),
|
||
|
args: vec![],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tlr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_B".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_alu".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("CORE_ALU_ADD".to_string())],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tlr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_set".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("MEM_ALLOC_PTR".to_string())],
|
||
|
},
|
||
|
]),
|
||
|
Instruction::Dot => Ok(vec![
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_ld".to_string(),
|
||
|
args: vec![],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tlr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_set".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("CORE_MEM_OUT".to_string())],
|
||
|
},
|
||
|
]),
|
||
|
Instruction::Emit => Ok(vec![
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_ld".to_string(),
|
||
|
args: vec![],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tlr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_set".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("CORE_MEM_CHR".to_string())],
|
||
|
},
|
||
|
]),
|
||
|
Instruction::Space => Ok(vec![
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_rset".to_string(),
|
||
|
args: vec![
|
||
|
hence::arg::Arg::Variable("CORE_REG_A".to_string()),
|
||
|
hence::arg::Arg::Char(' '),
|
||
|
],
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_set".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("CORE_MEM_CHR".to_string())],
|
||
|
},
|
||
|
]),
|
||
|
Instruction::Spaces => Ok(vec![]),
|
||
|
Instruction::Cr => Ok(vec![
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_rset".to_string(),
|
||
|
args: vec![
|
||
|
hence::arg::Arg::Variable("CORE_REG_A".to_string()),
|
||
|
hence::arg::Arg::Char('\n'),
|
||
|
],
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_set".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("CORE_MEM_CHR".to_string())],
|
||
|
},
|
||
|
]),
|
||
|
Instruction::StringPrint(x) => {
|
||
|
let loop_label = format!("loop_strings_{}", x);
|
||
|
let data_label = format!("data_strings_{}", x);
|
||
|
let data_end_label = format!("data_strings_end_{}", x);
|
||
|
|
||
|
Ok(vec![
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_rset".to_string(),
|
||
|
args: vec![
|
||
|
hence::arg::Arg::Variable("CORE_REG_B".to_string()),
|
||
|
hence::arg::Arg::Variable(data_label),
|
||
|
],
|
||
|
},
|
||
|
hence::parser::ast::Node::Label(loop_label.clone()),
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tsr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_B".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "get".to_string(),
|
||
|
arg: None,
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tlr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_set".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("CORE_MEM_CHR".to_string())],
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_rset".to_string(),
|
||
|
args: vec![
|
||
|
hence::arg::Arg::Variable("CORE_REG_A".to_string()),
|
||
|
hence::arg::Arg::Number(1),
|
||
|
],
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_alu".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("CORE_ALU_ADD".to_string())],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tlr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_B".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_rset".to_string(),
|
||
|
args: vec![
|
||
|
hence::arg::Arg::Variable("CORE_REG_A".to_string()),
|
||
|
hence::arg::Arg::Variable(data_end_label),
|
||
|
],
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_alu".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("CORE_ALU_GT".to_string())],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tlr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_cond_jump".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable(loop_label)],
|
||
|
},
|
||
|
])
|
||
|
}
|
||
|
Instruction::StringReference(x) => Ok(vec![
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "push".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable(format!("data_strings_end_{}", x))),
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "push".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable(format!("data_strings_{}", x))),
|
||
|
},
|
||
|
]),
|
||
|
Instruction::Count => Ok(vec![]),
|
||
|
Instruction::Not => Ok(vec![
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_ld".to_string(),
|
||
|
args: vec![],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tlr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_alu".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("CORE_ALU_NOT".to_string())],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tls".to_string(),
|
||
|
arg: None,
|
||
|
},
|
||
|
]),
|
||
|
Instruction::And => Ok(vec![
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "stack_transfer_alu".to_string(),
|
||
|
args: vec![],
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_alu".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("CORE_ALU_AND".to_string())],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tls".to_string(),
|
||
|
arg: None,
|
||
|
},
|
||
|
]),
|
||
|
Instruction::Nand => Ok(vec![
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "stack_transfer_alu".to_string(),
|
||
|
args: vec![],
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_alu".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("CORE_ALU_AND".to_string())],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tlr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_alu".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("CORE_ALU_NOT".to_string())],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tls".to_string(),
|
||
|
arg: None,
|
||
|
},
|
||
|
]),
|
||
|
Instruction::Or => Ok(vec![
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "stack_transfer_alu".to_string(),
|
||
|
args: vec![],
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_alu".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("CORE_ALU_OR".to_string())],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tls".to_string(),
|
||
|
arg: None,
|
||
|
},
|
||
|
]),
|
||
|
Instruction::Nor => Ok(vec![
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "stack_transfer_alu".to_string(),
|
||
|
args: vec![],
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_alu".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("CORE_ALU_OR".to_string())],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tlr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_alu".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("CORE_ALU_NOT".to_string())],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tls".to_string(),
|
||
|
arg: None,
|
||
|
},
|
||
|
]),
|
||
|
Instruction::Xor => Ok(vec![
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "stack_transfer_alu".to_string(),
|
||
|
args: vec![],
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_alu".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("CORE_ALU_XOR".to_string())],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tls".to_string(),
|
||
|
arg: None,
|
||
|
},
|
||
|
]),
|
||
|
Instruction::Xnor => Ok(vec![
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "stack_transfer_alu".to_string(),
|
||
|
args: vec![],
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_alu".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("CORE_ALU_XOR".to_string())],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tlr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_alu".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("CORE_ALU_NOT".to_string())],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tls".to_string(),
|
||
|
arg: None,
|
||
|
},
|
||
|
]),
|
||
|
Instruction::Lsh => Ok(vec![
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "stack_transfer_alu".to_string(),
|
||
|
args: vec![],
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_alu".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("CORE_ALU_LSH".to_string())],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tls".to_string(),
|
||
|
arg: None,
|
||
|
},
|
||
|
]),
|
||
|
Instruction::Rsh => Ok(vec![
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "stack_transfer_alu".to_string(),
|
||
|
args: vec![],
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_alu".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("CORE_ALU_RSH".to_string())],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tls".to_string(),
|
||
|
arg: None,
|
||
|
},
|
||
|
]),
|
||
|
Instruction::Compare => Ok(vec![
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "stack_transfer_alu".to_string(),
|
||
|
args: vec![],
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_alu".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("CORE_ALU_CMP".to_string())],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tls".to_string(),
|
||
|
arg: None,
|
||
|
},
|
||
|
]),
|
||
|
Instruction::Eq => Ok(vec![
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "stack_transfer_alu".to_string(),
|
||
|
args: vec![],
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_alu".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("CORE_ALU_EQ".to_string())],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tls".to_string(),
|
||
|
arg: None,
|
||
|
},
|
||
|
]),
|
||
|
Instruction::Neq => Ok(vec![
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "stack_transfer_alu".to_string(),
|
||
|
args: vec![],
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_alu".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("CORE_ALU_EQ".to_string())],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tlr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_alu".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("CORE_ALU_INV".to_string())],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tls".to_string(),
|
||
|
arg: None,
|
||
|
},
|
||
|
]),
|
||
|
Instruction::Lt => Ok(vec![
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "stack_transfer_alu".to_string(),
|
||
|
args: vec![],
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_alu".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("CORE_ALU_LT".to_string())],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tls".to_string(),
|
||
|
arg: None,
|
||
|
},
|
||
|
]),
|
||
|
Instruction::Leq => Ok(vec![
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "stack_transfer_alu".to_string(),
|
||
|
args: vec![],
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_alu".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("CORE_ALU_LEQ".to_string())],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tls".to_string(),
|
||
|
arg: None,
|
||
|
},
|
||
|
]),
|
||
|
Instruction::Gt => Ok(vec![
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "stack_transfer_alu".to_string(),
|
||
|
args: vec![],
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_alu".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("CORE_ALU_GT".to_string())],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tls".to_string(),
|
||
|
arg: None,
|
||
|
},
|
||
|
]),
|
||
|
Instruction::Geq => Ok(vec![
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "stack_transfer_alu".to_string(),
|
||
|
args: vec![],
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_alu".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("CORE_ALU_GEQ".to_string())],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tls".to_string(),
|
||
|
arg: None,
|
||
|
},
|
||
|
]),
|
||
|
Instruction::Min => Ok(vec![
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_ld".to_string(),
|
||
|
args: vec![],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tlr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_C".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tlr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_ld".to_string(),
|
||
|
args: vec![],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tlr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_B".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_alu".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("CORE_ALU_GT".to_string())],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tlr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tsr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_B".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tlrc".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_C".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tsr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_C".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tls".to_string(),
|
||
|
arg: None,
|
||
|
},
|
||
|
]),
|
||
|
Instruction::Max => Ok(vec![
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_ld".to_string(),
|
||
|
args: vec![],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tlr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_C".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tlr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_ld".to_string(),
|
||
|
args: vec![],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tlr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_B".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_alu".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("CORE_ALU_LT".to_string())],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tlr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tsr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_B".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tlrc".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_C".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tsr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_C".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tls".to_string(),
|
||
|
arg: None,
|
||
|
},
|
||
|
]),
|
||
|
Instruction::Boolean => Ok(vec![
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_ld".to_string(),
|
||
|
args: vec![],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tlr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_alu".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("CORE_ALU_BOL".to_string())],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tls".to_string(),
|
||
|
arg: None,
|
||
|
},
|
||
|
]),
|
||
|
Instruction::Invert => Ok(vec![
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_ld".to_string(),
|
||
|
args: vec![],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tlr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_alu".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("CORE_ALU_INV".to_string())],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tls".to_string(),
|
||
|
arg: None,
|
||
|
},
|
||
|
]),
|
||
|
Instruction::Random => Ok(vec![
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_alu".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("CORE_ALU_RND".to_string())],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tls".to_string(),
|
||
|
arg: None,
|
||
|
},
|
||
|
]),
|
||
|
Instruction::Plus => Ok(vec![
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "stack_transfer_alu".to_string(),
|
||
|
args: vec![],
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_alu".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("CORE_ALU_ADD".to_string())],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tls".to_string(),
|
||
|
arg: None,
|
||
|
},
|
||
|
]),
|
||
|
Instruction::OnePlus => Ok(vec![
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_ld".to_string(),
|
||
|
args: vec![],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tlr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_rset".to_string(),
|
||
|
args: vec![
|
||
|
hence::arg::Arg::Variable("CORE_REG_B".to_string()),
|
||
|
hence::arg::Arg::Number(1),
|
||
|
],
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_alu".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("CORE_ALU_ADD".to_string())],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tls".to_string(),
|
||
|
arg: None,
|
||
|
},
|
||
|
]),
|
||
|
Instruction::TwoPlus => Ok(vec![
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_ld".to_string(),
|
||
|
args: vec![],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tlr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_rset".to_string(),
|
||
|
args: vec![
|
||
|
hence::arg::Arg::Variable("CORE_REG_B".to_string()),
|
||
|
hence::arg::Arg::Number(2),
|
||
|
],
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_alu".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("CORE_ALU_ADD".to_string())],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tls".to_string(),
|
||
|
arg: None,
|
||
|
},
|
||
|
]),
|
||
|
Instruction::Minus => Ok(vec![
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "stack_transfer_alu".to_string(),
|
||
|
args: vec![],
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_alu".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("CORE_ALU_SUB".to_string())],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tls".to_string(),
|
||
|
arg: None,
|
||
|
},
|
||
|
]),
|
||
|
Instruction::OneMinus => Ok(vec![
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_ld".to_string(),
|
||
|
args: vec![],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tlr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_rset".to_string(),
|
||
|
args: vec![
|
||
|
hence::arg::Arg::Variable("CORE_REG_B".to_string()),
|
||
|
hence::arg::Arg::Number(1),
|
||
|
],
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_alu".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("CORE_ALU_SUB".to_string())],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tls".to_string(),
|
||
|
arg: None,
|
||
|
},
|
||
|
]),
|
||
|
Instruction::TwoMinus => Ok(vec![
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_ld".to_string(),
|
||
|
args: vec![],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tlr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_rset".to_string(),
|
||
|
args: vec![
|
||
|
hence::arg::Arg::Variable("CORE_REG_B".to_string()),
|
||
|
hence::arg::Arg::Number(2),
|
||
|
],
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_alu".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("CORE_ALU_SUB".to_string())],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tls".to_string(),
|
||
|
arg: None,
|
||
|
},
|
||
|
]),
|
||
|
Instruction::Times => Ok(vec![
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "stack_transfer_alu".to_string(),
|
||
|
args: vec![],
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_alu".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("CORE_ALU_MUL".to_string())],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tls".to_string(),
|
||
|
arg: None,
|
||
|
},
|
||
|
]),
|
||
|
Instruction::Divide => Ok(vec![
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "stack_transfer_alu".to_string(),
|
||
|
args: vec![],
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_alu".to_string(),
|
||
|
args: vec![hence::arg::Arg::Variable("CORE_ALU_DIV".to_string())],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tls".to_string(),
|
||
|
arg: None,
|
||
|
},
|
||
|
]),
|
||
|
Instruction::Mod => Ok(vec![]),
|
||
|
Instruction::Call(x) => match data.words.get(x) {
|
||
|
Some(w) => {
|
||
|
if w.times_used > 1 {
|
||
|
Ok(vec![hence::parser::ast::Node::MacroCall {
|
||
|
name: "call_stack_jump".to_string(),
|
||
|
args: vec![
|
||
|
hence::arg::Arg::Variable(format!("words_{}", w.id)),
|
||
|
hence::arg::Arg::Variable("OFFSET".to_string()),
|
||
|
],
|
||
|
}])
|
||
|
} else {
|
||
|
Ok(w.instructions
|
||
|
.iter()
|
||
|
.map(|ins| ins.compile(data))
|
||
|
.collect::<Result<Vec<hence::parser::ast::Body>>>()?
|
||
|
.into_iter()
|
||
|
.flatten()
|
||
|
.collect())
|
||
|
}
|
||
|
}
|
||
|
None => bail!("Unknown word: {}", x),
|
||
|
},
|
||
|
// Instruction::Call(x) => bail!("Unknown word: {}", x),
|
||
|
Instruction::AsmQuote(x) => Ok(hence::parser::parse(hence::lexer::lex(x)?)?.body),
|
||
|
// Instruction::Condition(x) => Ok(vec![]),
|
||
|
Instruction::Condition(x) => {
|
||
|
dbg!(x);
|
||
|
|
||
|
Ok(vec![])
|
||
|
}
|
||
|
|
||
|
Instruction::Multiple { instruction, count } => {
|
||
|
if *count == 0 {
|
||
|
Ok(vec![])
|
||
|
} else if *count == 1 {
|
||
|
Ok(instruction.compile(data)?)
|
||
|
} else {
|
||
|
match **instruction {
|
||
|
Instruction::Nop => Ok(Instruction::Nop.compile(data)?),
|
||
|
Instruction::Quit => Ok(Instruction::Quit.compile(data)?),
|
||
|
Instruction::Push(x) => Ok([
|
||
|
Instruction::Push(x).compile(data)?,
|
||
|
[hence::parser::ast::Node::Call {
|
||
|
name: "tls".to_string(),
|
||
|
arg: None,
|
||
|
}]
|
||
|
.into_iter()
|
||
|
.cycle()
|
||
|
.take(count - 1)
|
||
|
.collect(),
|
||
|
]
|
||
|
.concat()),
|
||
|
Instruction::Depth => Ok([
|
||
|
Instruction::Depth.compile(data)?,
|
||
|
Instruction::Multiple {
|
||
|
instruction: Box::new(Instruction::Dup),
|
||
|
count: count - 1,
|
||
|
}
|
||
|
.compile(data)?,
|
||
|
]
|
||
|
.concat()),
|
||
|
Instruction::Dup => Ok([
|
||
|
Instruction::Dup.compile(data)?,
|
||
|
[hence::parser::ast::Node::Call {
|
||
|
name: "tls".to_string(),
|
||
|
arg: None,
|
||
|
}]
|
||
|
.into_iter()
|
||
|
.cycle()
|
||
|
.take(count - 1)
|
||
|
.collect(),
|
||
|
]
|
||
|
.concat()),
|
||
|
Instruction::Swap => {
|
||
|
if count % 2 == 0 {
|
||
|
Ok(vec![])
|
||
|
} else {
|
||
|
Ok(Instruction::Swap.compile(data)?)
|
||
|
}
|
||
|
}
|
||
|
Instruction::Over => Ok([
|
||
|
Instruction::Over.compile(data)?,
|
||
|
(0..count - 1)
|
||
|
.flat_map(|n| {
|
||
|
if n % 2 == 0 {
|
||
|
vec![
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tsr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable(
|
||
|
"CORE_REG_A".to_string(),
|
||
|
)),
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tls".to_string(),
|
||
|
arg: None,
|
||
|
},
|
||
|
]
|
||
|
} else {
|
||
|
vec![
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tsr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable(
|
||
|
"CORE_REG_B".to_string(),
|
||
|
)),
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tls".to_string(),
|
||
|
arg: None,
|
||
|
},
|
||
|
]
|
||
|
}
|
||
|
})
|
||
|
.collect(),
|
||
|
]
|
||
|
.concat()),
|
||
|
Instruction::Rot => match count % 3 {
|
||
|
0 => Ok(vec![]),
|
||
|
1 => Ok(Instruction::Rot.compile(data)?),
|
||
|
2 => Ok(vec![
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_ld".to_string(),
|
||
|
args: vec![],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tlr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_ld".to_string(),
|
||
|
args: vec![],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tlr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_C".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_ld".to_string(),
|
||
|
args: vec![],
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tlr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_B".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tsr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tls".to_string(),
|
||
|
arg: None,
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tsr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_B".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tls".to_string(),
|
||
|
arg: None,
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tsr".to_string(),
|
||
|
arg: Some(hence::arg::Arg::Variable("CORE_REG_C".to_string())),
|
||
|
},
|
||
|
hence::parser::ast::Node::Call {
|
||
|
name: "tls".to_string(),
|
||
|
arg: None,
|
||
|
},
|
||
|
]),
|
||
|
x => bail!("Remainder of count % 3 cannot be higher than 3: {}", x),
|
||
|
},
|
||
|
Instruction::Nip => Ok([
|
||
|
vec![hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_ld".to_string(),
|
||
|
args: vec![],
|
||
|
}],
|
||
|
[hence::parser::ast::Node::Call {
|
||
|
name: "pop".to_string(),
|
||
|
arg: None,
|
||
|
}]
|
||
|
.into_iter()
|
||
|
.cycle()
|
||
|
.take(*count)
|
||
|
.collect(),
|
||
|
vec![hence::parser::ast::Node::Call {
|
||
|
name: "tls".to_string(),
|
||
|
arg: None,
|
||
|
}],
|
||
|
]
|
||
|
.concat()),
|
||
|
Instruction::I | Instruction::J => Ok([
|
||
|
instruction.compile(data)?,
|
||
|
[hence::parser::ast::Node::Call {
|
||
|
name: "tls".to_string(),
|
||
|
arg: None,
|
||
|
}]
|
||
|
.into_iter()
|
||
|
.cycle()
|
||
|
.take(count - 1)
|
||
|
.collect(),
|
||
|
]
|
||
|
.concat()),
|
||
|
Instruction::Fetch => Ok([
|
||
|
vec![hence::parser::ast::Node::MacroCall {
|
||
|
name: "std_ld".to_string(),
|
||
|
args: vec![],
|
||
|
}],
|
||
|
[hence::parser::ast::Node::Call {
|
||
|
name: "get".to_string(),
|
||
|
arg: None,
|
||
|
}]
|
||
|
.into_iter()
|
||
|
.cycle()
|
||
|
.take(*count)
|
||
|
.collect(),
|
||
|
vec![hence::parser::ast::Node::Call {
|
||
|
name: "tls".to_string(),
|
||
|
arg: None,
|
||
|
}],
|
||
|
]
|
||
|
.concat()),
|
||
|
Instruction::Space | Instruction::Cr => Ok([
|
||
|
instruction.compile(data)?,
|
||
|
[hence::parser::ast::Node::Call {
|
||
|
name: "set".to_string(),
|
||
|
arg: None,
|
||
|
}]
|
||
|
.into_iter()
|
||
|
.cycle()
|
||
|
.take(count - 1)
|
||
|
.collect(),
|
||
|
]
|
||
|
.concat()),
|
||
|
_ => {
|
||
|
let compiled = instruction.compile(data)?;
|
||
|
let len = compiled.len() * count;
|
||
|
Ok(compiled.into_iter().cycle().take(len).collect())
|
||
|
}
|
||
|
}
|
||
|
}
|
||
|
}
|
||
|
}
|
||
|
}
|
||
|
}
|
||
|
|
||
|
impl Instruction {
|
||
|
pub fn from_word(word: &str) -> Option<Self> {
|
||
|
match word.to_lowercase().as_str() {
|
||
|
"nop" => Some(Instruction::Nop),
|
||
|
"debug" => Some(Instruction::Debug),
|
||
|
"quit" => Some(Instruction::Quit),
|
||
|
"drop" => Some(Instruction::Drop),
|
||
|
"depth" => Some(Instruction::Depth),
|
||
|
"pick" => Some(Instruction::Pick),
|
||
|
"dup" => Some(Instruction::Dup),
|
||
|
"swap" => Some(Instruction::Swap),
|
||
|
"over" => Some(Instruction::Over),
|
||
|
"rot" => Some(Instruction::Rot),
|
||
|
"nip" => Some(Instruction::Nip),
|
||
|
"i" => Some(Instruction::I),
|
||
|
"j" => Some(Instruction::J),
|
||
|
"tuck" => Some(Instruction::Tuck),
|
||
|
"@" => Some(Instruction::Fetch),
|
||
|
"?" => Some(Instruction::FetchPrint),
|
||
|
"!" => Some(Instruction::Store),
|
||
|
"+!" => Some(Instruction::PlusStore),
|
||
|
"-!" => Some(Instruction::MinusStore),
|
||
|
"cells" => Some(Instruction::Cells),
|
||
|
"allot" => Some(Instruction::Allot),
|
||
|
"." => Some(Instruction::Dot),
|
||
|
"emit" => Some(Instruction::Emit),
|
||
|
"space" => Some(Instruction::Space),
|
||
|
"spaces" => Some(Instruction::Spaces),
|
||
|
"cr" => Some(Instruction::Cr),
|
||
|
"count" => Some(Instruction::Count),
|
||
|
"not" => Some(Instruction::Not),
|
||
|
"and" => Some(Instruction::And),
|
||
|
"nand" => Some(Instruction::Nand),
|
||
|
"or" => Some(Instruction::Or),
|
||
|
"nor" => Some(Instruction::Nor),
|
||
|
"xor" => Some(Instruction::Xor),
|
||
|
"xnor" => Some(Instruction::Xnor),
|
||
|
"lshift" => Some(Instruction::Lsh),
|
||
|
"rshift" => Some(Instruction::Rsh),
|
||
|
"compare" => Some(Instruction::Compare),
|
||
|
"=" => Some(Instruction::Eq),
|
||
|
"!=" => Some(Instruction::Neq),
|
||
|
"<" => Some(Instruction::Lt),
|
||
|
"<=" => Some(Instruction::Leq),
|
||
|
">" => Some(Instruction::Gt),
|
||
|
">=" => Some(Instruction::Geq),
|
||
|
"min" => Some(Instruction::Min),
|
||
|
"max" => Some(Instruction::Max),
|
||
|
"boolean" => Some(Instruction::Boolean),
|
||
|
"invert" => Some(Instruction::Invert),
|
||
|
"random" => Some(Instruction::Random),
|
||
|
"+" => Some(Instruction::Plus),
|
||
|
"1+" => Some(Instruction::OnePlus),
|
||
|
"2+" => Some(Instruction::TwoPlus),
|
||
|
"-" => Some(Instruction::Minus),
|
||
|
"1-" => Some(Instruction::OneMinus),
|
||
|
"2-" => Some(Instruction::TwoMinus),
|
||
|
"*" => Some(Instruction::Times),
|
||
|
"/" => Some(Instruction::Divide),
|
||
|
"mod" => Some(Instruction::Mod),
|
||
|
_ => None,
|
||
|
}
|
||
|
}
|
||
|
}
|