2023-03-23 16:59:10 +00:00
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.include "$lib/core.asm"
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.include "$lib/std.asm"
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.include "$lib/main.asm"
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2023-03-24 20:13:40 +00:00
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2023-03-23 16:59:10 +00:00
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.define MEM_LOOP_I, CORE_MEM_MEM
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.define MEM_LOOP_J, (MEM_LOOP_I + 1)
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2023-03-23 16:59:10 +00:00
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.define MEM_CALL_STACK_LEN, 16
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.define MEM_CALL_STACK_PTR, (MEM_LOOP_J + 1)
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.define MEM_CALL_STACK_END, (MEM_CALL_STACK_PTR + MEM_CALL_STACK_LEN)
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.define MEM_ALLOC_PTR, MEM_CALL_STACK_END
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.std_rset CORE_REG_A, MEM_CALL_STACK_PTR
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.std_set MEM_CALL_STACK_PTR
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.std_rset CORE_REG_A, (MEM_ALLOC_PTR + 1)
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.std_set MEM_ALLOC_PTR
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2023-03-23 16:59:10 +00:00
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.jump_main
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call_stack_jump:
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.std_get MEM_CALL_STACK_PTR
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tlr CORE_REG_A
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.std_rset CORE_REG_B, 1
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.std_alu CORE_ALU_ADD
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tlr CORE_REG_A
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tlr CORE_REG_B
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.std_set MEM_CALL_STACK_PTR
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tsr CORE_REG_D
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tlr CORE_REG_A
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tsr CORE_REG_B
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set
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tsr CORE_REG_C
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tlr CORE_REG_PC
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return_call_stack_jump:
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.std_get MEM_CALL_STACK_PTR
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tlr CORE_REG_A
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tlr CORE_REG_C
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.std_rset CORE_REG_B, 1
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.std_alu CORE_ALU_SUB
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tlr CORE_REG_A
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.std_set MEM_CALL_STACK_PTR
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tsr CORE_REG_C
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get
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tlr CORE_REG_PC
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.macro stack_transfer_alu
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.std_ld
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tlr CORE_REG_B
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.std_ld
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tlr CORE_REG_A
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.endmacro
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.macro call_stack_jump, call_stack_jump_arg_0_label, call_stack_jump_arg_1_offset
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.std_rset CORE_REG_C, call_stack_jump_arg_0_label
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.std_rset CORE_REG_D, (call_stack_jump_arg_1_offset + 7)
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ts call_stack_jump
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tlr CORE_REG_PC
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.endmacro
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.macro return_call_stack_jump
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.std_jump return_call_stack_jump
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.endmacro
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; data
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; strings
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data_strings_0:
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; original : "test\n"
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; size : 5
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.bytes 0x74
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.bytes 0x65
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.bytes 0x73
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.bytes 0x74
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.bytes 0x0a
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data_strings_end_0:
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data_strings_1:
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; original : "jdsafhjfnjfn\n"
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; size : 13
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.bytes 0x6a
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.bytes 0x64
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.bytes 0x73
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.bytes 0x61
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.bytes 0x66
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.bytes 0x68
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.bytes 0x6a
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.bytes 0x66
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.bytes 0x6e
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.bytes 0x6a
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.bytes 0x66
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.bytes 0x6e
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.bytes 0x0a
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data_strings_end_1:
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; conditions
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; words
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; main
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.def_main
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ts NULL ; reset tmp
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.std_rset CORE_REG_B, data_strings_0
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loop_strings_0:
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tsr CORE_REG_B
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get
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tlr CORE_REG_A
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.std_set CORE_MEM_CHR
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.std_rset CORE_REG_A, 1
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.std_alu CORE_ALU_ADD
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tlr CORE_REG_B
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.std_rset CORE_REG_A, data_strings_end_0
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.std_alu CORE_ALU_GT
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tlr CORE_REG_A
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.std_cond_jump loop_strings_0
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.std_rset CORE_REG_B, data_strings_1
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loop_strings_1:
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tsr CORE_REG_B
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get
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tlr CORE_REG_A
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.std_set CORE_MEM_CHR
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.std_rset CORE_REG_A, 1
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.std_alu CORE_ALU_ADD
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tlr CORE_REG_B
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.std_rset CORE_REG_A, data_strings_end_1
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.std_alu CORE_ALU_GT
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tlr CORE_REG_A
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.std_cond_jump loop_strings_1
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push 40
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push 2
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.stack_transfer_alu
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.std_alu CORE_ALU_ADD
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tls
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dbg
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.std_ld
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tlr CORE_REG_A
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.std_rset CORE_REG_B, 2
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.std_alu CORE_ALU_ADD
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tls
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dbg
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push 65456
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dbg
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.std_stop
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