From cf1af6b412d3511e7888a474f51db1131ee606c8 Mon Sep 17 00:00:00 2001
From: Dominic Grimm <dominic.grimm@gmail.com>
Date: Wed, 7 Sep 2022 12:28:26 +0200
Subject: [PATCH] Add emit word

---
 henceforth/examples/test.asm               |  43 +++++++++++++++++++++
 henceforth/examples/test.bin               | Bin 0 -> 32768 bytes
 henceforth/examples/test.fth               |   2 +-
 henceforth/src/lib/compiler/instruction.rs |  23 ++++++-----
 4 files changed, 58 insertions(+), 10 deletions(-)
 create mode 100644 henceforth/examples/test.asm
 create mode 100644 henceforth/examples/test.bin

diff --git a/henceforth/examples/test.asm b/henceforth/examples/test.asm
new file mode 100644
index 0000000..8325d62
--- /dev/null
+++ b/henceforth/examples/test.asm
@@ -0,0 +1,43 @@
+.include "$lib/core.asm"
+.include "$lib/std.asm"
+.include "$lib/main.asm"
+.define MEM_CALL_STACK, CORE_MEM_MEM
+.macro stack_transfer_alu
+.std_ld
+tlr CORE_REG_B
+.std_ld
+tlr CORE_REG_A
+.endmacro
+.macro call_word, call_word_arg_0_label
+ts (OFFSET + 14)
+tlr CORE_REG_A
+ts MEM_CALL_STACK
+set
+ts call_word_arg_0_label
+tlr CORE_REG_PC
+.endmacro
+.macro return_word
+.std_get MEM_CALL_STACK
+tlr CORE_REG_PC
+.endmacro
+.jump_main
+data:
+data_strings:
+words:
+main:
+.main main
+push 10
+tss
+tls
+tss
+tls
+.std_ld
+tlr CORE_REG_A
+.std_set CORE_MEM_CHR
+.std_ld
+tlr CORE_REG_A
+.std_set CORE_MEM_CHR
+.std_ld
+tlr CORE_REG_A
+.std_set CORE_MEM_CHR
+.std_stop
\ No newline at end of file
diff --git a/henceforth/examples/test.bin b/henceforth/examples/test.bin
new file mode 100644
index 0000000000000000000000000000000000000000..3a9fe762bdf2575aa723d1d34513536b2a5c90a0
GIT binary patch
literal 32768
zcmeIuu?c`c5Jb^ERt;?WKyWdzNDC28b32eXKbiPtzpKT%A8*?db6)NIo*bjX2oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
q2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+z%K<drg{Ln-VVe7

literal 0
HcmV?d00001

diff --git a/henceforth/examples/test.fth b/henceforth/examples/test.fth
index 8455af2..8646ba3 100644
--- a/henceforth/examples/test.fth
+++ b/henceforth/examples/test.fth
@@ -1 +1 @@
-." t;;;;;;;;;;;;;;;;;;;;;;est\n"
+0x0a dup dup emit emit emit
diff --git a/henceforth/src/lib/compiler/instruction.rs b/henceforth/src/lib/compiler/instruction.rs
index 1be274f..60e34aa 100644
--- a/henceforth/src/lib/compiler/instruction.rs
+++ b/henceforth/src/lib/compiler/instruction.rs
@@ -174,14 +174,6 @@ impl compiler::Compilable<compiler::Data, hence::parser::ast::Body> for Instruct
                 },
             ]),
             Instruction::Swap => Ok(vec![
-                // hence::parser::ast::Node::Call {
-                //     name: "ld".to_string(),
-                //     arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
-                // },
-                // hence::parser::ast::Node::Call {
-                //     name: "ld".to_string(),
-                //     arg: Some(hence::arg::Arg::Variable("CORE_REG_B".to_string())),
-                // },
                 hence::parser::ast::Node::MacroCall {
                     name: "std_ld".to_string(),
                     args: vec![],
@@ -242,7 +234,20 @@ impl compiler::Compilable<compiler::Data, hence::parser::ast::Body> for Instruct
                     args: vec![hence::arg::Arg::Variable("CORE_MEM_OUT".to_string())],
                 },
             ]),
-            Instruction::Emit => Ok(vec![]),
+            Instruction::Emit => Ok(vec![
+                hence::parser::ast::Node::MacroCall {
+                    name: "std_ld".to_string(),
+                    args: vec![],
+                },
+                hence::parser::ast::Node::Call {
+                    name: "tlr".to_string(),
+                    arg: Some(hence::arg::Arg::Variable("CORE_REG_A".to_string())),
+                },
+                hence::parser::ast::Node::MacroCall {
+                    name: "std_set".to_string(),
+                    args: vec![hence::arg::Arg::Variable("CORE_MEM_CHR".to_string())],
+                },
+            ]),
             Instruction::Space => Ok(vec![]),
             Instruction::Spaces => Ok(vec![]),
             Instruction::Cr => Ok(vec![